1. Field of the Invention
The present invention relates to a crown capacitor, and particularly to a high capacitance crown capacitor for a DRAM cell and a method of manufacturing the same.
2. Description of the Related Arts
Referring to FIG. 1, a conventional DRAM cell consists of a transistor T and a capacitor C. The source of the transistor T is connected to a corresponding bit line BL. The drain of the transistor T is connected to the bottom electrode of the capacitor C. The gate of the transistor is connected to a corresponding word line WL. The top electrode of the capacitor C is biased with a constant voltage source. A dielectric layer is arranged between the bottom electrode and the top electrode. As known to those skilled in the art, the bottom capacitor C is provided for data storage. Therefore, the capacitor requires a large capacitance to prevent data loss and lower the refresh rate.
For a conventional DRAM of less than 1MB capacity, a two-dimensional capacitor structure is utilized for data storage. This capacitor structure is well known as a planar-type capacitor. However, in order to provide a capacitance large enough for data storage, the planar-type capacitor occupies a very large base area. Therefore, this structure can not be applied in a high-density DRAM process.
Accordingly, some three-dimensional capacitor structures, such as a trench-type or stack structure, have been developed to satisfy the requirements of highly integrated DRAM devices of more than 16MB. However, the formation of trench-type structures results in defects in the substrate, thereby increasing current leakage and affecting the device performance. Moreover, since the etching rate of the trench decreases as the aspect ratio increases, the process becomes more difficult, and the DRAM productivity is reduced. Therefore, the trench-type structure is not useful in practical applications. The stack capacitor, on the other hand, is free of all the problems mentioned above. It is therefore very popular in small-dimensional memory fabrication and has attracted a lot of attention regarding structure optimization.
Among all the kinds of stack capacitors, the crown capacitor in which an electrode has an upright extending portion to provide a very large area for data storage is favored for highly-integrated memory devices, especially for those have a capacity of more than 64MB.
The conventional process of forming a crown capacitor for a DRAM cell will be described in accompaniment with the drawings of FIGS. 2A through 2C.
Referring to FIG. 2A, a semiconductor substrate 200 is provided. The substrate 200 has a field oxide layer 202 formed thereon to define an active region. A gate electrode G including a gate oxide layer 204, a polysilicon layer 210, a tungsten silicide layer (WSi.sub.x) 212, a silicon oxide layer 214, and a silicon oxynitride layer (SiO.sub.x N.sub.y) 216 is formed on the active region. A lightly doped source/drain region is formed using the gate electrodes G as a mask, usually by implanting an N-type impurity such as arsenic or phosphorous. A gate spacer 217 is formed on the sidewall of the gate structure G by depositing and anisotropically etching back an insulation layer. Then the complete source/drain region 208 is formed by implanting an N-type impurity into the substrate 200 using -he gate structure G and the spacer 217 as a mask.
After forming the transistors on the substrate 200, an insulation layer 218 and a stop layer 222 are successively formed over the substrate 200. A contact hole 224 is formed in the insulation layer 218 and the stop layer 222 to expose a portion of the source/drain region 208. Then a first conducting layer 226 is formed on the stop layer and fills the contact hole 224. Then a sacrificial layer 228 is formed on the first conducting layer 226.
Referring to FIG. 2B, the sacrificial layer 228 and the first conducting layer 226 are patterned and etched to the surface of the stop layer 222.
Turning to FIG. 2C, a second insulation layer 230 is conformally formed over the patterned sacrificial layer 228, patterned first conducting layer, and stop layer 222.
Referring to FIG. 2D, the second inducting layer 230 is etched back to the surface of the stop layer 222; thereby, the top surface of the sacrificial layer 228 is exposed.
Turning to FIG. 2E, the remaining sacrificial layer 228 is removed; thereby, the remaining first conducting layer 230 and second conducting layer 226 form the bottom electrode of the crown capacitor 240.
Referring to FIG. 2F, a dielectric layer 242 and a third conducting layer 244 used as top electrode of the crown capacitor are successively formed over the bottom electrode 240. As a result, a crown capacitor according to the conventional method is formed.
Obviously, the conventional method only uses one patterned sacrificial layer 228 as a model to form the bottom electrode; thereby, the sidewall of the bottom electrode is smooth and can't provide high capacitance.